As integrated circuit (IC) technology continues to evolve, the use within ICs of wide multi-signal buses, such as data buses, becomes more prevalent. Generally speaking, such buses consume large amounts of limited routing resources, causing routing problems for both the bus and other signal connections within an IC. Also, as the functional capacity of ICs increase, the interconnections required between circuit “blocks” of the IC increase as well, thus exacerbating the routing problem.
FIG. 1 exemplifies this problem by way of a simplified diagram. Three circuit blocks 2a, 2b and 2c are each connected to a signal bus comprised of signals 0 through n. Each block thus contains n+1 separate ports P, each of which is to be connected to the corresponding signal of the signal bus. Unfortunately, as is often the case, the ports P of each block 2 do not align with each other, but are instead ordered somewhat randomly within each block 2. As a result, each signal connection 1 requires the use of several vertical and horizontal routing resources, called “tracks,” to implement the necessary connections. As more vertical and horizontal tracks are used, more routing resources are consumed, resulting in fewer routing options for other IC signals. In many cases, routing of such buses often causes enough congestion within the tracks to make routing of the entire IC problematic.
To help alleviate such routing congestion, IC designers sometimes force the placement of the ports within each block in an orderly fashion. An example of this port placement is shown in FIG. 2. Blocks 3a, 3b and 3c each employ ports P which are placed in order from signal 0 through signal n. As a result, each signal connection 1 requires the use of a single vertical routing track and no horizontal routing tracks, thus consuming substantially fewer routing resources than what were required with the random port ordering of FIG. 1.
However, such orderly port placement within each block often creates a burden on the IC designer in terms of time and effort to architect each block to minimize routing resources. Additionally, many block designs simply preclude such orderly port alignment.
From the foregoing, a need exists for the ability to optimize the routing of IC inter-block signals among blocks utilizing somewhat randomly placed ports. Such ability would reduce the substantial amount of routing resources typically required for signal buses while eliminating the burden of orderly port placement on the IC designer.